One of the conventional processes for formation of semiconductor memory cells is the process for formation of "COB" (capacitor over bit line) cells, an example of which is illustrated in FIG. 1. Such a COB cell is disclosed in "IEDM 90-655, 27.3.1 to 27.3.4".
FIGS. 1A, 1B and 1D are sectional views taken along line 1A--1A of FIG. 1F, and FIG. 1C is a sectional view taken along line 1C--1C of FIG. 1F.
Referring to FIG. 1A, rectangular active area 22 (see FIG. 1F) is formed by applying a polysilicon buffered LOCOS process, followed by formation of a gate oxide. Then, word line 3 is formed. After capacitor buried contact hole 51 is opened, local interconnects 5 are formed using polysilicon.
Then, as shown in FIG. 1B, after insulating layer 8 is deposited, a bit line contact is opened and filled with doped polysilicon plug 6. Tungsten polycide bit-line 7 is formed to run above the active areas.
FIG. 1C is a sectional view taken along line 1C--1C of FIG. 1F. As shown in FIG. 1C, insulating inter-layer 81 is formed on the bit line and is planarized.
After opening the capacitor contact, "HSG" (hemispherical grain) polysilicon storage electrode 9 is formed. HSG polysilicon storage node 9 is connected to the active area through the capacitor contact and local interconnect 5.
Then, as shown in FIG. 1D, a capacitor dielectric layer and capacitor plate electrode are formed. After insulating inter-layer 82 is deposited, primary metal wiring 55 is formed.
FIG. 1F illustrates the layout of the memory cell, and FIG. 1E is a perspective view of a part of the memory cell.
In the memory cell formed in the above described manner, the height of storage electrode 9 typically has to be over 4000.ANG. in order to obtain sufficient capacitance for each memory cell, and, therefore, a height difference exists between the memory cell and the surrounding portions before carrying out the primary metal wiring. As a result of the height difference, patterning errors are increased when carrying out subsequent processes (such as photo-lithographic and etch processes).